An OS-Based Alternative to Full Hardware Coherence on Tiled Chip-Multiprocessors
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Date
2008Author
Fensch, Christian
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Abstract
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors
(CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a
larger number of cores. Tiled CMPs offer better scalability by integrating relatively simple cores
with a lightweight point-to-point interconnect. However, such interconnects make snooping
impractical and, thus, require alternative solutions to cache coherence.
This thesis proposes a novel, cost-effective hardware mechanism to support shared-memory
parallel applications that forgoes hardware maintained cache coherence. The proposed mech-
anism is based on the key ideas that mapping of lines to physical caches is done at the page
level with OS support and that hardware supports remote cache accesses. It allows only some
controlled migration and replication of data and provides a sufficient degree of flexibility in the
mapping through an extra level of indirection between virtual pages and physical tiles.
The proposed tiled CMP architecture is evaluated on the SPLASH-2 scientific benchmarks
and ALPBench multimedia benchmarks against one with private caches and a distributed direc-
tory cache coherence mechanism. Experimental results show that the performance degradation
is as little as 0%, and 16% on average, compared to the cache coherent architecture across all
benchmarks for 16 and 32 processors.