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dc.contributor.advisorO'Boyle, Michael
dc.contributor.advisorFranke, Bjorn
dc.contributor.authorDubach, Christophe
dc.date.accessioned2010-10-06T10:21:10Z
dc.date.available2010-10-06T10:21:10Z
dc.date.issued2009
dc.identifier.urihttp://hdl.handle.net/1842/3867
dc.description.abstractDesigning new microprocessors is a time consuming task. Architects rely on slow simulators to evaluate performance and a significant proportion of the design space has to be explored before an implementation is chosen. This process becomes more time consuming when compiler optimisations are also considered. Once the architecture is selected, a new compiler must be developed and tuned. What is needed are techniques that can speedup this whole process and develop a new optimising compiler automatically. This thesis proposes the use of machine-learning techniques to address architecture/compiler co-design. First, two performance models are developed and are used to efficiently search the design space of amicroarchitecture. These models accurately predict performance metrics such as cycles or energy, or a tradeoff of the two. The first model uses just 32 simulations to model the entire design space of new applications, an order of magnitude fewer than state-of-the-art techniques. The second model addresses offline training costs and predicts the average behaviour of a complete benchmark suite. Compared to state-of-the-art, it needs five times fewer training simulations when applied to the SPEC CPU 2000 and MiBench benchmark suites. Next, the impact of compiler optimisations on the design process is considered. This has the potential to change the shape of the design space and improve performance significantly. A new model is proposed that predicts the performance obtainable by an optimising compiler for any design point, without having to build the compiler. Compared to the state-of-the-art, this model achieves a significantly lower error rate. Finally, a new machine-learning optimising compiler is presented that predicts the best compiler optimisation setting for any new program on any new microarchitecture. It achieves an average speedup of 1.14x over the default best gcc optimisation level. This represents 61% of the maximum speedup available, using just one profile run of the application.en
dc.language.isoenen
dc.publisherThe University of Edinburghen
dc.relation.hasversionChristophe Dubach, Timothy M. Jones, and Michael F. P. O’Boyle “Microarchitectural Design Space Exploration Using An Architecture-Centric Approach”. In: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40), 2007en
dc.relation.hasversionChristophe Dubach, Timothy M. Jones, and Michael F.P. O’Boyle. “Exploring and Predicting the Architecture/Optimising Compiler Co-Design Space”. In: Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2008.en
dc.subjectcomputer architectureen
dc.subjectmachine-learning techniquesen
dc.subjectmicroarchitectureen
dc.titleUsing machine-learning to efficiently explore the architecture/compiler co-design spaceen
dc.typeThesis or Dissertationen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePhD Doctor of Philosophyen


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