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dc.contributor.advisorBrown, Nicholas
dc.contributor.advisorJackson, William
dc.contributor.authorJamieson, Maurice
dc.date.accessioned2022-11-24T13:38:56Z
dc.date.available2022-11-24T13:38:56Z
dc.date.issued2022-11-24
dc.identifier.urihttps://hdl.handle.net/1842/39522
dc.identifier.urihttp://dx.doi.org/10.7488/era/2772
dc.description.abstractMicro-core architectures are intended to deliver high performance at a low overall power consumption by combining many simple central processing unit (CPU) cores, with an associated small amount of memory, onto a single chip. This technology is not only of great interest for embedded, Edge and IoT applications but also for High-Performance Computing (HPC) accelerators. However, micro-core architectures are difficult to program and exploit, not only because each technology is different, with its own idiosyncrasies, but also because they each present a different low-level interface to the programmer. Furthermore, micro-cores have very constrained amounts of on-chip, scratchpad memory (often around 32KB), further hampering programmer productivity by requiring the programmer to manually manage the regular loading and unloading of data from the host to the device during program execution. To help address these issues, dynamic languages such as Python have been ported to several micro-core architectures but these are often delivered as interpreters with the associated performance penalty over natively compiled languages, such as C. The research questions for this thesis target four areas of concern for dynamic programming languages on micro-core architectures: (RQ1) how to manage the limited on-chip memory for data, (RQ2) how to manage the limited on-chip memory for code, (RQ3) how to address the low runtime performance of virtual machines and (RQ4) how to manage the idiosyncratic architectures of micro-core architectures. The focus of this work is to address these concerns whilst maintaining the programmer productivity benefits of dynamic programming languages, using ePython as the research vehicle. Therefore, key areas of design (such as abstractions for offload) and implementation (novel compiler and runtime techniques for these technologies) are considered, resulting in a number of approaches that are not only applicable to the compilation of Python codes but also more generally to other dynamic languages on micro-cores architectures. RQ1 was addressed by providing support for kernels with arbitrary data size through high-level programming abstractions that enable access to the memory hierarchies of micro-core devices, allowing the deployment of real-world applications, such as a machine learning code to detect cancer cells in full-sized scan images. A new abstract machine, Olympus, addressed RQ2 by supporting the compilation of dynamic languages, such as Python, to micro-core native code. Olympus enables ePython to close the kernel runtime performance gap with native C, matching C for the LINPACK and an iterative Fibonacci benchmark, and to provide, on average, around 75\% of native C runtime performance across four benchmarks running on a set of eight CPU architectures. Olympus also addresses RQ3 by providing dynamic function loading, supporting kernel codes larger than the on-chip memory, whilst still retaining the runtime performance benefits of native code generation. Finally, RQ4 was addressed by the Eithne benchmarking framework which not only enabled a single benchmarking code to be deployed, unchanged, across different CPU architectures, but also provided the underlying communications framework for Olympus. The portability of end-user ePython codes and the underlying Olympus abstract machine were validated by running a set of four benchmarks on eight different CPU architectures, from a single codebase.en
dc.contributor.sponsorEngineering and Physical Sciences Research Council (EPSRC)en
dc.language.isoenen
dc.publisherThe University of Edinburghen
dc.relation.hasversionMaurice Jamieson and Nick Brown, “Performance of the Vipera framework for DSLs on micro-core architectures,” Euro-Par 2022: DSL-HPC workshop, 2022en
dc.relation.hasversionMaurice Jamieson and Nick Brown, “Compact native code generation for dynamic languages on micro-core architectures,” in Proceedings of the 30th ACM SIGPLAN International Conference on Compiler Construction, ser. CC 2021. Association for Computing Machinery, 2021, pp. 131–140en
dc.relation.hasversionMaurice Jamieson, Nick Brown, and Sihang Liu, “Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro core architectures using ePython,” in Proceedings of the 19th Python in Science Conference : SciPy 2020, 2020, pp. 97–105en
dc.relation.hasversionMaurice Jamieson and Nick Brown,“Benchmarking micro-core architectures for detecting disasters at the edge,” in 2020 IEEE/ACM HPC for Urgent Decision Making (UrgentHPC), 2020, pp. 27–35en
dc.relation.hasversionMaurice Jamieson and Nicholas Brown, “High level programming abstractions for leveraging hierarchical memories with micro-core architectures,” Journal of Parallel and Distributed Computing, vol. 138, pp. 128-138, 2020en
dc.relation.hasversionNicholas Brown and Maurice Jamieson, “Leveraging hierarchical memories for micro-core architectures”, Extended abstract 5th International Conference on Exascale Applications and Software, Edinburgh, United Kingdom, 2018en
dc.subjectmicro-core architecturesen
dc.subjectdynamic programming languagesen
dc.subjectePythonen
dc.subjectEithne benchmarking frameworken
dc.subjectOlympus abstract machineen
dc.titleEnabling high performance dynamic language programming for micro-core architecturesen
dc.typeThesis or Dissertationen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePhD Doctor of Philosophyen


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