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dc.contributor.advisorTopham, Nigel
dc.contributor.advisorAspinall, David
dc.contributor.authorSalem, Heba
dc.date.accessioned2023-04-25T13:38:13Z
dc.date.available2023-04-25T13:38:13Z
dc.date.issued2023-04-25
dc.identifier.urihttps://hdl.handle.net/1842/40532
dc.identifier.urihttp://dx.doi.org/10.7488/era/3298
dc.description.abstractHistorically, hardware was thought to be inherently secure and trusted due to its obscurity and the isolated nature of its design and manufacturing. In the last two decades, however, hardware trust and security have emerged as pressing issues. Modern day hardware is surrounded by threats manifested mainly in undesired modifications by untrusted parties in its supply chain, unauthorized and pirated selling, injected faults, and system and microarchitectural level attacks. These threats, if realized, are expected to push hardware to abnormal and unexpected behaviour causing real-life damage and significantly undermining our trust in the electronic and computing systems we use in our daily lives and in safety critical applications. A large number of detective and preventive countermeasures have been proposed in literature. It is a fact, however, that our knowledge of potential consequences to real-life threats to hardware trust is lacking given the limited number of real-life reports and the plethora of ways in which hardware trust could be undermined. With this in mind, run-time monitoring of hardware combined with active mitigation of attacks, referred to as trustworthy computing on untrustworthy hardware, is proposed as the last line of defence. This last line of defence allows us to face the issue of live hardware mistrust rather than turning a blind eye to it or being helpless once it occurs. This thesis proposes three different frameworks towards trustworthy computing on untrustworthy hardware. The presented frameworks are adaptable to different applications, independent of the design of the monitored elements, based on autonomous security elements, and are computationally lightweight. The first framework is concerned with explicit violations and breaches of trust at run-time, with an untrustworthy on-chip communication interconnect presented as a potential offender. The framework is based on the guiding principles of component guarding, data tagging, and event verification. The second framework targets hardware elements with inherently variable and unpredictable operational latency and proposes a machine-learning based characterization of these latencies to infer undesired latency extensions or denial of service attacks. The framework is implemented on a DDR3 DRAM after showing its vulnerability to obscured latency extension attacks. The third framework studies the possibility of the deployment of untrustworthy hardware elements in the analog front end, and the consequent integrity issues that might arise at the analog-digital boundary of system on chips. The framework uses machine learning methods and the unique temporal and arithmetic features of signals at this boundary to monitor their integrity and assess their trust level.en
dc.language.isoenen
dc.publisherThe University of Edinburghen
dc.relation.hasversionH. Salem and N. Topham, “Trustworthy computing on untrustworthy and Trojan infected on-chip interconnects,” 2021 IEEE European Test Symposium (ETS), 2021, pp. 1-2, doi: 10.1109/ETS50041.2021.9465416.en
dc.relation.hasversionH. Salem and N. Topham, “Detecting denial-of-service hardware Trojans in DRAM-based memory systems,” 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2021, pp. 1-6, doi: 10.1109/ICECS53924.2021.9665634.en
dc.subjectcomputer chipsen
dc.subjectcounterfeitingen
dc.subjectmonitoring of hardware trust and securityen
dc.subjecton-chip communicationen
dc.subjectsecurity of hardwareen
dc.subjectmicroarchitectural level attacksen
dc.titleTowards trustworthy computing on untrustworthy hardwareen
dc.typeThesis or Dissertationen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePhD Doctor of Philosophyen


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