SPAD-based time of flight pixel designs for large scale arrays

Abstract

Since early research into the avalanche multiplication of p-n junctions in the early 1960’s, the Single Photon Avalanche Diode (SPAD) has become a popular detector element for 3D Time of Flight (TOF) Complementary Metal-Oxide Semiconductor (CMOS) image sensors. SPADs are ideal candidates for high-speed, time-resolved imaging systems because of their shot-noise limited photon detection capability and high temporal resolution.

Today, SPAD-based TOF image sensors are used in both consumer and industrial applications ranging from biometric identification to automotive Light Detection and Ranging (LIDAR), to terrain mapping and medical imaging. However, the high temporal resolution of the detectors and the desire for high frame rates from the sensors result in a high data rate and large power consumption. These issue are exacerbated by the fact that the sensors are often embedded into hand-held battery powered devices, where power consumption is an even greater limiting factor. They also limit the maximum sensor resolutions that are feasible.

The goal of this research is to explore new pathways to enable high-resolution and low power SPAD-based TOF image sensors. The research hypothesis is that analogue domain pixels – contrary to their digital counterparts – can achieve a small pixel pitch and low power operation while maintaining high count depths and multi-bin photon detection capability. For this purpose, two key pixel building blocks are investigated: a photon counting circuit based on an analogue Charge Transfer Amplifier (CTA) and a two-bin time-gate circuit implemented with a dynamic comparator.

Leveraging these two building blocks, three low power pixels were designed: a 2-bin and 4-bin pixel with a standard source-follower readout and a 2-bin self-referenced pixel with a modified readout mechanism to remove first order non-linearities and combat pixel-to-pixel variations. The pixel pitches range from 4.8 µm to 7.2 µm and include the smallest SPAD-based analogue domain pixel to date. Additionally, a low-swing clock distribution network to further reduce the power consumption of the pixel architectures is enabled by the dynamic comparator time gate.

Two test chips were designed and fabricated in ST Microelectronics 40 nm Front-side Illuminated CMOS process. The first chip (E4) contains 3x3 pixel test structures for the three different pixel designs. The pixels achieve multi-bin operation at a count depth of 7 - 9 bit and have a power consumption as low as 8.6 - 13.9 nW/MHz SPAD rate. A second test chip (QA8) was fabricated as a 96 x 64 rolling shutter image sensor for long-range TOF measurements. The sensor implements a 128-bin on-chip analogue histogram based on the CTA and employs a self-referenced Analogue-to-Digital Converter (ADC). Preliminary results from this sensor architecture are discussed.