AI hardware topologies for symbolic processing

Abstract

Unlike conventional numerical processing, symbolic processing involves the manipulation of symbols and expressions, which is fundamental for applications in artificial intelligence such as problem-solving and language understanding. They normally require a knowledge base memory for storing and manipulating information, and the memory searching abilities in these systems are crucial for optimising energy consumption and resource utilisation. Especially when operating a sophisticated (and large) data repository, it is necessary to access and process data effectively and efficiently. This thesis investigated hardware platforms for accelerating knowledge base systems that stores symbolic information. The presented accelerators are complex systems featuring deep hierarchies. This work designed a graph database accelerator supporting "infinitely labellable graphs" (supporting labels, and labels of labels, etc.). Throughout the process the project made contributions to the individual memory bitcell level, developed an array-level dually-addressable memory (DAM) module (that is, both content-addressable and address-addressable) and contributed a mid-scale structure that allows fast processing of graph database information across multiple DAMs. More specifically, it combines RRAM devices in nanotechnology into the CMOS technology, applying RRAM as a standard memory storage element and performing in-memory computing to benefit from hardware efficiency.

The array-level dually-addressable system operates with a clock speed of 875MHz in 180nm technology. It reports an average of 4.15fJ/operation per bit including energy consumption for 64x64 core and front-line peripherals. Further to an upgraded system, the knowledge base memory core supports 512 entries of 512-bit data and achieves 43.38mW at peak when searching for a pair of information. This special modular architecture brings flexibility to the memory to be tailored to specific data sizes.