Franke, Bjoern

Topham, Nigel

Wagstaff, Harry

Engineering and Physical Sciences Research Council (EPSRC)

2016-01-20T16:04:49Z

2016-01-20T16:04:49Z

2015-11-26

As computer systems become increasingly complex and diverse, so too do the architectures they implement. This leads to an increase in complexity in the tools used to design new hardware and software. One particularly important tool in hardware and software design is the Instruction Set Simulator, which is used to prototype new architectures and hardware features, verify hardware, and test and debug software. Many Architecture Description Languages exist which facilitate the description of new architectural or hardware features, and generate a tools such as simulators. However, these typically suffer from poor performance, are difficult to test effectively, and may be limited in functionality. This thesis considers three objectives when developing Instruction Set Simulators: performance, correctness, and completeness, and presents techniques which contribute to each of these. Performance is obtained by combining Dynamic Binary Translation techniques with a novel analysis of high level architecture descriptions. This makes use of partial evaluation techniques in order to both improve the translation system, and to improve the quality of the translated code, leading a performance improvement of over 2.5x compared to a naïve implementation. This thesis also presents techniques which contribute to the correctness objective. Each possible behaviour of each described instruction is used to guide the generation of a test case. Constraint satisfaction techniques are used to determine the necessary instruction encoding and context for each behaviour to be produced. It is shown that this is a significant improvement over benchmark-driven testing, and this technique has led to the discovery of several bugs and inconsistencies in multiple state of the art instruction set simulators. Finally, several challenges in ‘Full System’ simulation are addressed, contributing to both the performance and completeness objectives. Full System simulation generally carries significant performance costs compared with other simulation strategies. Crucially, instructions which access memory require virtual to physical address translation and can now cause exceptions. Both of these processes must be correctly and efficiently handled by the simulator. This thesis presents novel techniques to address this issue which provide up to a 1.65x speedup over a state of the art solution.

http://hdl.handle.net/1842/14162

en

The University of Edinburgh

H. Wagstaff, M. Gould, B. Franke, and N. Topham, "Early Partial Evaluation in a JIT-Compiled, Retargetable Instruction Set Simulator Generated From a High-Level Architecture Description", in Proceedings of the 50th Annual Design Automation Conference (DAC’50), 2013

T. Spink, H.Wagstaff, B. Franke, and N. Topham, "Efficient Code Generation in a Region-Based Dynamic Binary Translator", in Proceedings of the 2014 ACM SIGPLAN/SIGBED conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES’14), 2014

H.Wagstaff, T. Spink, and B. Franke, "Automated ISA Branch Coverage Analysis and Test Case Generation for Retargetable Instruction Set Simulators", in Proceedings of the 2014 International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES’14), 2014

T. Spink, H. Wagstaff, B. Franke, and N. Topham, "Efficient Asynchronous Interrupt Handling in a Full-System Instruction Set Simulator", under review for the 2015 ACM SIGPLAN/SIGBED conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES’15), 2015

T. Spink, H. Wagstaff, B. Franke, and N. Topham, "Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator", under review for the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS’15), 2015

computer architecture

Instruction Set Simulator

Dynamic Binary Translation

high level architecture descriptions

correctness objective

From high level architecture descriptions to fast instruction set simulators

Thesis or Dissertation

Doctoral

PhD Doctor of Philosophy