Edinburgh Research Archive

Transforming acoustic hologram with CMOS Active Matrix Drivers

Item Status

Restricted Access

Embargo End Date

2022-11-28

Abstract

Acoustic holograms facilitate biocompatible, contactless 3-D manipulations of nanometer to micron-scale particles and particle groups. This has the potential to permit many biomedical applications, notably including tissue engineering. In the search for real-time, high resolution 3-D manipulation, a reconfigurable acoustic hologram with high resolution is required. However, existing acoustic holographic techniques can only partly fulfil this requirement. Therefore, a potential solution is proposed in the form of on-chip integration of CMOS circuits and piezoelectric ultrasonic transducers, named ‘Piezoelectric-on-CMOS’ (PoC) integration. This thesis presents a proof-of-concept of a new type of CMOS matrix driver for the future ‘PoC’ integration solution. It has the capability of generating synchronized output signals with phases which are individually tunable in real time whilst maintaining the low system complexity associated with a reduced port count. This allows the large-scale integration with ultrasonic transducers to provide dynamic reconfigurable acoustic holograms with higher holographic resolution compared to directly-wired phased arrays. Evidence of the matrix driver functions, and scalability are provided by the results of electrical and acoustical test of phased arrays constructed with prototype 1 × 9 driver array chips. These have demonstrated the feasibility and potential of the ‘PoC’ integration. This thesis additionally presents a SPICE modelling method for broadband, high quality modelling of piezoelectric ultrasonic transducer array elements, which is essential for matrix driver design simulations and future ‘PoC’ integration. An alternative CMOS matrix driver design is also reported, implementing a novel programmable oscillator. This design provides unique features such as tunable output signal duty cycle and tunable phase control resolution. To demonstration its functioning, flexibility and scalability, a prototype 1 × 4 driver array chip has been fabricated and tested.

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