Analysis and optimisation of high throughput digital silicon photomultipliers

Abstract

Large area detectors for time correlated single photon counting (TCSPC) are nowadays being implemented in CMOS technology to benefit a large variety of applications including positron emission tomography (PET) and 3D laser ranging (LiDAR), exploiting the advanced timing and counting capabilities inside single chips. Single photon avalanche diodes (SPADs) and silicon photomultipliers (SiPMs) represent a great option to realise such detectors thanks to their exceptional timing resolution and the ability to be arranged into arrays. Recently, digital SiPMs (dSiPMs) have been introduced to improve the integration with CMOS technology overcoming limitations on the readout of analogue SiPMs and thus improving the photon resolution of the detector. This work presents a 14GSamples=s time-to-digital converter (TDC) to improve the throughput of dSiPM sensors commonly limited by the sampling rate of the timing/counting readout circuitry. The converter has been demonstrated on a test chip in 130nm CMOS imaging technology paired with a novel XOR-based 32 32 SPAD array single-channel detector. The overall achieved throughput equals 1GEvents=s demonstrated in a direct time-of-flight LiDAR experiment. By acquiring a number of photons significantly higher than one per laser pulse, this approach represents the first example in TCSPC of an input rate and conversion rate both higher than the excitation rate. The following part of the work presents a modelling analysis on how to match the achieved high sampling rate / throughput of the single-channel TDC to the performance of a SPAD array. The impact of a selection of dSiPM design parameters, such as photon detection efficiency, dead time and size of the SPAD cell, number of cells per single-channel, digital N-to-1 combining network and channel bandwidth, on the overall sensor throughput and the dynamic range has been characterised thanks to a computational Monte-Carlo simulator and useful equations describing each of the processes in the sensing chain. The pile-up effect, i.e. the event-loss causing non-linear distortions on the output signal, has been characterised on each element of the dSiPM and optimisations have been proposed. Event losses in the SPAD cells due to dead time, in the digital combining network due to network dead time and single-channel bandwidth have all been identified, simulated and described by analytical equations. All the results coming from the theoretical analysis have been reproduced in real dSiPM design thanks to a reconfigurable test chip realised in the same 130nm CMOS imaging technology specifically to validate the proposed theory. The manufactured test chip provides the very first direct comparison between OR-based and XOR-based single-channel dSiPM sensors highlighting the promising timing and counting performance of the newly introduced XOR-based dSiPM. Direct evidence of pile-up distortions and subsequent reduction through design optimisations are demonstrated. A recommended design flow for next generation dSiPMs is proposed at the end of the publication.