Franke, Bjoern

Leather, Hugh

Spink, Thomas

Engineering and Physical Sciences Research Council (EPSRC)

2017-11-02T14:04:06Z

2017-11-02T14:04:06Z

2017-07-07

Hardware virtualisation is the provision of an isolated virtual environment that represents real physical hardware. It enables operating systems, or other system-level software (the guest), to run unmodified in a “container” (the virtual machine) that is isolated from the real machine (the host). There are many use-cases for hardware virtualisation that span a wide-range of end-users. For example, home-users wanting to run multiple operating systems side-by-side (such as running a Windows® operating system inside an OS X environment) will use virtualisation to accomplish this. In research and development environments, developers building experimental software and hardware want to prototype their designs quickly, and so will virtualise the platform they are targeting to isolate it from their development workstation. Large-scale computing environments employ virtualisation to consolidate hardware, enforce application isolation, migrate existing servers or provision new servers. However, the majority of these use-cases call for same-architecture virtualisation, where the architecture of the guest and the host machines match—a situation that can be accelerated by the hardware-assisted virtualisation extensions present on modern processors. But, there is significant interest in virtualising the hardware of different architectures on a host machine, especially in the architectural research and development worlds. Typically, the instruction set architecture of a guest platform will be different to the host machine, e.g. an ARM guest on an x86 host will use an ARM instruction set, whereas the host will be using the x86 instruction set. Therefore, to enable this cross-architecture virtualisation, each guest instruction must be emulated by the host CPU—a potentially costly operation. This thesis presents a range of techniques for accelerating this instruction emulation, improving over a state-of-the art instruction set simulator by 2:64x. But, emulation of the guest platform’s instruction set is not enough for full hardware virtualisation. In fact, this is just one challenge in a range of issues that must be considered. Specifically, another challenge is efficiently handling the way external interrupts are managed by the virtualisation system. This thesis shows that when employing efficient instruction emulation techniques, it is not feasible to arbitrarily divert control-flow without consideration being given to the state of the emulated processor. Furthermore, it is shown that it is possible for the virtualisation environment to behave incorrectly if particular care is not given to the point at which control-flow is allowed to diverge. To solve this, a technique is developed that maintains efficient instruction emulation, and correctly handles external interrupt sources. Finally, modern processors have built-in support for hardware virtualisation in the form of instruction set extensions that enable the creation of an abstract computing environment, indistinguishable from real hardware. These extensions enable guest operating systems to run directly on the physical processor, with minimal supervision from a hypervisor. However, these extensions are geared towards same-architecture virtualisation, and as such are not immediately well-suited for cross-architecture virtualisation. This thesis presents a technique for exploiting these existing extensions, and using them in a cross-architecture virtualisation setting, improving the performance of a novel cross-architecture virtualisation hypervisor over state-of-the-art by 2:5x.

http://hdl.handle.net/1842/25377

en

The University of Edinburgh

Tom Spink, Harry Wagstaff and Björn Franke “Hardware Accelerated Cross-Architecture Full-System Virtualization” In ACM Transactions on Architecture and Code Optimization (TACO) 13, 4, Article 36, October 2016

Tom Spink, Harry Wagstaff and Björn Franke “Efficient Asynchronous Interrupt Handling in a Full-system Instruction Set Simulator” In Proceedings of the 2016 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems (LCTES’16), Santa Barbara, CA, USA, June 2016.

Tom Spink, Harry Wagstaff, Björn Franke and Nigel Topham “Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator” In Proceedings of the 2015 International Conference on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS’15), Samos Island, Greece, July 2015.

Tom Spink, Harry Wagstaff, Björn Franke and Nigel Topham “Efficient code generation in a region-based dynamic binary translator.” In Proceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems (LCTES’14), Edinburgh, UK, June 2014.

Harry Wagstaff, Tom Spink and Björn Franke “Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators” In Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES’14), New Delhi, June 2014.

virtualisation

simulation

Efficient cross-architecture hardware virtualisation

Thesis or Dissertation

Doctoral

PhD Doctor of Philosophy